A 650 MHz DDFS for stretch processing radar in 130nm BiCMOS process

A quadrature 650 MHz direct digital frequency synthesizer (DDFS) with linear phase and frequency modulation capabilities is realized in a 130nm BiCMOS process. The DDFS supports stretch processing pulse compression for a single chip radar transceiver (RoC). The design features a partial dynamic rotation (PDR) Cordinate Rotation DIgital Computer (CORDIC) for the phase to sine and cosine mapping functions (SCMF), a 32 bit phase accumulator with a 0.23 Hz frequency resolution at native operating frequency, 32 bit linear frequency modulation (LFM), 14-bit linear phase modulation (LPM), additive dithering for randomization of phase truncation spurs, two inverse sinc functions for zero-order hold (ZOH) transfer function correction of the DAC, stretch processing radar control circuitry and two twelve bit CMOS current steering DACs.