Characteristics and process stability of complete electrical interconnection structures for a low cost interposer technology

Silicon interposers enable the heterogeneous integration of high performance systems. This paper focuses on interconnections from one chip to a neighboring chip in a side-by-side interposer approach. We investigate the performance of interconnections on a typical silicon interposer with polymer applied to the redistribution layer on both sides using electromagnetic simulations. The simulations are valued by measurements. Our measurements show that microstrip lines with <0.3 dB/mm insertion loss at 30 GHz can be achieved with a typical polymer based interposer process. In contrast to other work we extend the microstrip line model with pads on both ends to form a complete interconnection. Our investigations show that an insertion loss of <0.55 dB/mm can be achieved assuming dense interconnections. We investigate the impact of technological variations during the manufacturing process of a silicon interposer. This is important to ensure electrical functionality ( signal and power integrity) of the system in mass production. The results on technology variations during the manufacturing process of an interposer show that variations of 20 % in trace width and trace height are changing the characteristic impedance of the line, but do not significantly affect the signal integrity of sufficiently long lines. In contrast, variations of 20 % in polymer height and polymer permittivity in the redistribution layer have more influence on signal integrity of sufficiently long interposer interconnections.