A 20 Gb/S 0.4 Pj/B Energy-Efficient Transmitter Driver Architecture Utilizing Constant G(M)

This paper presents an energy-efficient transmitter driver architecture that is suitable for high-speed operation. By employing an inverter with resistive feedback as a driver cell, the proposed driver topology can overcome the disadvantage of conventional voltage-mode drivers, namely, that the pre-driver power consumption increases as the data rate increases. This driver topology has another advantage that equalization can be easily realized. In order to evaluate the performance of the proposed driver, a PRBS generator, a serializer, and a half-rate clock generator are included in the prototype chip. The proposed driver and equalizer circuit operate reliably at a data rate of up to 20 Gb/s exhibiting an energy efficiency of 0.4 pJ/b for an output swing of 250 mV(ppd).