A SoPC design of a real-time high-definition stereo matching algorithm.

This paper proposed an System-on-Programmable-Chip (SoPC) architecture to implement a stereo matching algorithm based on a kind of sparse census transform in a FPGA chip which can provide a high-definition dense disparity map in real-time. The circuits of the algorithm were modeled by the Matlab-based DSP Builder. The whole algorithm circuits were implemented in pipelined structure. It can process many different sizes of stereo pair images through a configuration interface. The maximum horizon resolution of stereo images is 2048. The algorithm core runs at 6MHz, and 30 frames of 1396x1110 disparity maps can be obtained in one second with 5x5 matching window and maximum 64 disparity pixels.