Development of a low power 5.12 Gbps data serializer and wireline transmitter circuit for the VeloPix chip

A new front-end chip (VeloPix) is being developed for the readout of the silicon vertex locator detector (VELO) in the LHCb experiment after the upgrade scheduled for 2018. The chip with an active area of 2 cm(2) will run at a very high hit rate (up to 500 Mhitcm(-2)sec(-1)) and will transmit large amounts of data (> 15 Gbit-per-sec) over a 1 meter low-mass copper cable. A test chip with a prototype of a 5.12 Gbps Data Serializer and Wireline Transmitter (line driver) circuit has been submitted in 130 nm CMOS technology. A multiplexer based architecture has been chosen for the implementation the serializer block. In the proposed solution a 16-to-1 round-robin multiplexer selects one bit of data at a time from either a posedge triggered section or a negedge triggered section of a 16-bit input register clocked at 320 MHz. The serializer consumes only 15 mW of power and the line driver with pre-emphasis consumes 45 mW. In this paper the circuit design is explained and some measured results are presented.