The reliability of through silicon via under thermal cycling
Electronic Packaging Technology（2015）
摘要
Through silicon via (TSV) is a critical element for three-dimensional (3D) integration of devices in vertically multilevel stack-die microelectronic packages. In this paper, the microstructure evolution of TSV-Cu under thermal cycling was studied and the topography of TSVs under thermal cycling tests was examined by white light interferometer. It was found that the Cu was intrude inside the Si die during the test, and the intrusion height increased with cycle time and leveled off at 0.72μm and 0.53μm for upside and backside after 210 cycles, respectively. Besides, the Cu intrusion height at the Cu/Si interface is greater than that in the middle of Cu bar. in addition, cracks were observed at SiO2/Ta barrier interface and between BEOL line and Cu vias. It suggests that diffusional creep of the interface is the key for Cu via intrusion, the residual stress and thermal stress drive the interfacial sliding at interfaces.
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关键词
copper,diffusion creep,integrated circuit reliability,integrated circuit testing,light interferometers,silicon compounds,tantalum,thermal stresses,three-dimensional integrated circuits,3D integration,BEOL line,Cu,Cu vias,SiO2-Ta barrier interface,SiO2-Ta,TSV-Cu,diffusional creep,interfacial sliding,intrusion height,microstructure evolution,residual stress,size 0.53 mum,size 0.72 mum,thermal cycling tests,thermal stress,three-dimensional integration,through silicon via reliability,vertically multilevel stack-die microelectronic packages,white light interferometer,TSV,intrusion,thermal cycling
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