Hybrid multiple constant multiplication for FPGAs

The multiple constant multiplication (MCM) is a frequently used operation in many digital signal processing applications like digital filters. Mapping MCM to modern heterogeneous field programmable gate arrays (FPGAs) is commonly done by either using embedded multipliers or a carry-chain dominated method using additions, subtractions and bit shifts. The use of embedded multipliers is restricted by their quantity and word size. In particular, large coefficients as required for floating point MCM may need lots of embedded multipliers for each single constant. This work presents an optimization method which is able to include a user-defined number of embedded multipliers into a fully pipelined add/shift based MCM operation. Multiplier results can be shared between several constants for resource reduction. The algorithm can be either used for finding a trade-off between DSP and logic resources or to realize large MCM blocks with less DSP resources.