CVD-Co/Cu(Mn) integration and reliability for 10 nm node
Interconnect Technology Conference(2013)
摘要
In studying integrated dual damascene hardware at 10 nm node dimensions, we identified the mechanism for Co liner enhancement of Cu gap-fill to be a wetting improvement of the PVD Cu seed, rather than a local nucleation enhancement for Cu plating. We then show that Co “divot” (top-comer slit void defect) formation can be suppressed by a new wet chemistry, in turn eliminating divot-induced EM degradation. Further, we confirm a relative decrease in Cu-alloy seed proportional resistivity impact compared to scattering at scaled dimensions, and finally we address the incompatibility between the commonly-used carbonyl-based CVD-Co process with Cu-alloy seed EM performance This problem is due to oxidation of Ta(N) barriers at the TaN/CVD-Co interface by carbonyl-based CVD processes, which then consumes alloy atoms before they can segregate at the Cu/cap interface. We show that O-free CVD-Co may solve this problem. The above solutions may then enable CVD-Co/Cu-alloy seed integration in advanced nodes.
更多查看译文
关键词
chemical vapour deposition,cobalt alloys,copper alloys,integrated circuit interconnections,integrated circuit metallisation,integrated circuit reliability,manganese alloys,tantalum compounds,co-cu(mn),pvd,ta(n),commonly used carbonyl based cvd process,copper plating,divot-induced em degradation,integrated dual damascene hardware,liner enhancement,local nucleation enhancement,seed proportional resistivity impact,size 10 nm,top-comer slit void defect,wet chemistry,wetting improvement,reliability,chemistry,corrosion,degradation,resistance,manganese
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要