A 9b, 1.12ps resolution 2.5b/stage pipelined time-to-digital converter in 65nm CMOS using time-register

VLSI Circuits（2013）

引用 36|浏览7

暂无评分

摘要

This paper presents a 2.5b/stage pipelined time-to-digital converter (TDC). For pipelined operation, a novel time-register is proposed which is capable of storing and adding time information with a clock signal. Together with a time-amplifier, a 9-bit synchronous pipelined TDC is implemented which consists of three 2.5b stages and a 3b flash TDC. A prototype chip fabricated in 65nm CMOS achieves 1.12ps of time resolution at 250Msps while consuming 15.4mW, which results in the best FoM among the state-of-the-art TDCs.

查看译文

关键词

cmos integrated circuits,amplifiers,pipeline processing,time-digital conversion,cmos,fom,clock signal,pipelined time-to-digital converter,power 15.4 mw,prototype chip fabrication,size 65 nm,storage capacity 2.5 bit,storage capacity 9 bit,synchronous pipelined tdc,time 1.12 ps,time resolution,time-amplifier,time-register,2.5b/stage,pll and adpll,pipeline,time amplifier,time register,time storage,time-to-digital converter (tdc),very large scale integration,pipelines,synchronization,calibration,tin

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要