Profitability-based power allocation for speculative multithreaded systems

With the shrinking of transistors continuing to follow Moore's Law and the non-scalability of conventional out- of-order processors, multi-core systems are becoming the design choice for industry. Performance extraction is thus largely alleviated from the hardware and placed on the pro- grammer/compiler camp, who now have to expose Thread LevelParallelism (TLP) to the underlyingsystem in the form of explicitly parallel applications. Unfortunately, parallel programming is hard and error- prone. The programmer has to parallelize the work, per- form the data placement, and deal with thread synchroniza- tion. Systems that support speculative multithreaded execu- tion like Thread Level Speculation (TLS), offer an interest- ing alternative since they relieve the programmer from the burden of parallelizing applications and correctly synchro- nizing them. Since systems that support speculative multithreading usually treat all threads equally, they are energy-inefficient. This inefficiency stems from the fact that speculation occa- sionally fails and, thus, power is spent on threads that will have to be discarded. In this paper we propose a power al- location scheme for TLS systems, based on Dynamic Volt- age and Frequency Scaling (DVFS), that tries to remedy this inefficiency. More specifically, we propose a profitability- based power allocation scheme, where we "steal" power from non-profitable threads and use it to speed up more use- ful ones. We evaluate our techniques for a state-of-the-art TLS system and show that, with minimal hardware support, they lead to improvements in ED of up to 39.6% with an �This work was supported in part by EPSRC under grant EP/G000697/1 and the EC under grant HiPEAC IST-004408. †This work was done before the author joined Intel, while being