56nm-pitch low-k/Cu dual-damascene interconnects integration with sidewall image transfer (SIT) patterning scheme

Masayoshi Tagami,Koji Shimada,Yansheng Yin,Michio Ishikawa,C Waskiewicz,St Chen,H Shobha,Eiichi Soda,Nicole Saulnier,John C Arnold,Matthew E Colburn,T Usui,T Spooner

Interconnect Technology Conference（2012）

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摘要

Three metal level 56nm-pitch Cu dual damascene interconnects in k2.7 low-k ILD have been demonstrated by using sidewall-image-transfer (SIT) patterning scheme to investigate the feasibility of the SIT process for sub 50nm-pitch technology node. 45nm-pitch line resistance (R) and capacitance (C) simulation are performed to estimate the R-C variation for double patterning schemes. The photoresist mandrel SIT process for 56nm-pitch Cu line is investigated to develop the constant line pitch and less line edge roughness (LER). The basic electrical properties such as line open/short and via chain open/short yields are ~100%. The 56nm-pitch R-C variation is comparable to simulated 80nm-pitch R-C variation. The SIT patterning process is a strong candidate to improve the R-C variation for sub50nm-pitch technology nodes.

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关键词

rc circuits,copper,integrated circuit interconnections,photoresists,cu,r-c variation,sit patterning scheme,chain open-short yield,constant line pitch,double patterning scheme,electrical property,less ler,less line edge roughness,line capacitance simulation,line open-short yield,line resistance simulation,low-k ild,low-k-cu dual-damascene interconnection integration,photoresist mandrel sit process,sidewall image transfer patterning scheme,size 45 nm,size 50 nm,size 56 nm,size 80 nm,three metal level dual damascene interconnection,lithography,tin,resistance,resists,capacitance

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