Compact physical models for chip and package power and ground distribution networks for gigascale integration (GSI)
Lake Buena Vista, FL(2008)
摘要
For the first time, compact physical models are derived in this work that enable quick package- and chip-scale calculations of the power supply noise and incorporate the distributed natures of on-chip power/ground grids and package-level power/ground planes. Designers can use these models to perform chip/package co-design for power distribution networks and tradeoff multiple design considerations such as metal resource allocation on chip and in package, decoupling capacitor insertion and I/O allocation. Such studies can be performed during early stages of design, even when detailed physical design information is not available. The models are used to model a ceramic package designed by IBM, and it is found that there is less than 10% difference between the model predictions and the commercial tool SPEED 2000 when predicting the peak noise value and time of occurrence. The models can have 10times speed-up compared to SPEED 2000.
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关键词
ceramic packaging,distribution networks,integrated circuit design,i/o allocation,ibm,speed 2000,ceramic package,chip-scale calculations,chip/package co-design,compact physical models,decoupling capacitor insertion,gigascale integration,ground distribution networks,metal resource allocation,on-chip power/ground grids,package power,package-level power/ground planes,peak noise value,physical design information,power supply noise,quick package-scale calculations,network on a chip,decoupling capacitor,resource allocation,chip scale packaging,power systems,predictive models,physical model,physical design,voltage,chip,resource management
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