Design optimization of gate-silicided ESD NMOSFETs in a 45nm bulk CMOS technology

Alvarez, D.,Chatty, K.,Russ, C.,Abou-Khalil, M.J.

Anaheim, CA（2007）

引用 6|浏览0

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摘要

Decrease of the drain silicide-blocking-to-gate spacing in gate-silicided-ESD-NMOSFETs improves the TLP and HBM failure levels up to 30%, while no effect is observed when decreasing the source silicide-blocking-to-gate spacing. Failure analysis and simulation results show that current crowding in the drain silicide region accounts for the difference in failure current for the devices.

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关键词

CMOS integrated circuits,MOSFET,electrostatic discharge,failure analysis,HBM failure,TLP failure,bulk CMOS technology,current crowding,design optimization,drain silicide region,drain silicide-blocking-to-gate spacing,failure analysis,gate-silicided ESD NMOSFET,size 45 nm,source silicide-blocking-to-gate spacing,

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