Temperature-Aware Placement for SOCs

ó Dramatic rises in the power consumption and inte- gration density of contemporary systems-on-chip (SoCs) have led to the need for careful attention to chip-level thermal integrity. High temperatures or uneven temperature distributions may result not only in reliability issues, but also timing failures, due to the temperature-dependent nature of chip time-to-failure and delay, respectively. To resolve these issues, high quality, accurate thermal modeling and analysis, and thermally-oriented place- ment optimizations, are essential prior to tapeout. This paper rst presents an overview of thermal modeling and simulation methods such as nite-differ ence time domain, nite element, model reduction, random walk, and Green-function based algo- rithms, that are appropriate for use in placement algorithms. Next, 2D and 3D thermal-aware placement algorithms such as matrix-synthesis, simulated annealing, partition-driven, and force directed are presented. Finally, future trends and challenges are described.