Semiconductor Process and Device Modeling: a graduate course/undergraduate elective in microelectronic engineering at RIT

Semiconductor Process and Device Modeling is a senior / graduate level course on the application of simulation tools for design and verification of microelectronic processes and operation of semiconductor devices. The goal of the course is to provide a more in-depth understanding of complex processes and device physics through the use of simulation tools. Silvaco-SUPREM (Athena/Atlas) is the primary process and device simulation tool used throughout the course. The course explores the various models that are used for front-end silicon processes, emphasizing the importance of complex interactions and 2-D effects as devices are scaled deep-submicron. Electrical device simulation and parameter extraction provides a study on how changes in the device structure can influence device operation. The investigation continues to the circuit level through modifications of SPICE model parameters and analog circuit simulation. I. INTRODUCTION Process and device simulation is an important part of the microelectronic engineering curriculum at RIT. The first part of this paper will give an overview of the topics discussed in the course, and how the simulation tools are used to investigate various process and device effects. In addition to the laboratory exercises, individual student projects that have been investigated will also be discussed. The second part will present results from a recent full-class investigation on developing a baseline 2µm CMOS process. Various processing considerations were discussed as the baseline process was assembled. A tolerance analysis was performed using Athena/Atlas simulation in order to develop a robust process that yielded consistent device results. Once a final process flow was decided, electrical parameters (SPICE level-2) were extracted from electrical simulation results in a manual/iterative fashion. The operation of actual fabricated device structures (fabricated at RIT, outside of this class) was used to verify the simulation models. The baseline process was then modified as necessary, using simulation to explore how to scale the devices down to submicron dimensions. Simulated device performance results were compared to theoretical and empirical predictions.