Manufacturable Embedded Cmos 6t-Sram Technology With High-K Gate Dielectric Device For System-On-Chip Applications

Cb Oh,Hs Kang,Hj Ryu,Mh Oh,Hs Jung,Ys Kim,Jh Lee, Ni Lee,Kh Cho, Dh Lee, Th Yang, Is Cho,Hk Kang,Yw Kim, Kp Suh

San Francisco, CA, USA(2002)

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摘要
Manufacturable embedded CMOS 6T-SRAM with the HfO2-Al2O3 dielectric for system-on-chip (SoC) applications is successfully demonstrated for the first time in the semiconductor industry. The possibility of the high-k gate dielectric in low power SoC applications is suggested. 0.11mum NFET and PFET devices with thin high-k gate dielectric have 470 and 150muA/mum at Ioff=0.1nA/um and Vdd=1.2V, respectively. Inversion thickness of NFET and PFET are 2.4nm and 2.7nm, respectively. Gate leakage current of the high-k is 1000 times lower than that of the oxynitride at the accumulation region. Static noise margin of 2.14mum(2) 6T-SRAM bit cell is about 300mV at Vdd=1.2V. 6T-SRAM chip yield of the high-k is comparable to that of the oxynitride. The post nitridation after high-k film deposition is very important to the yield of the SRAM chips due to the suppression of the PFET boron penetration. Stand-by current of the SRAM chips with the high-k is shown to be a decreases of 60% compared with the oxynitride.
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cmos memory circuits,sram chips,dielectric thin films,low-power electronics,system-on-chip,0.11 micron,1.2 v,hfo/sub 2/-al/sub 2/o/sub 3/ high-k gate dielectric,nfet device,pfet device,boron penetration,chip yield,embedded cmos 6t-sram technology,gate leakage current,inversion thickness,low-power system-on-chip,post nitridation,semiconductor manufacturing,stand-by current,static noise margin,low power electronics,chip,leakage current,system on chip
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