Flushing-enabled loop pipelining for high-level synthesis

Design Automation Conference(2014)

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摘要
Loop pipelining is a widely-accepted technique in high-level synthesis to enable pipelined execution of successive loop iterations to achieve high performance. Existing loop pipelining methods provide inadequate support for pipeline flushing. In this paper, we study the problem of enabling flushing in pipeline synthesis and examine its implications in scheduling and binding. We propose novel techniques for synthesizing a conflict-aware flushing-enabled pipeline that is robust against potential resource collisions. Experiments with real-life benchmarks show that our methods significantly reduce the possibility of resource collisions compared to conventional approaches while conserving hardware resources and achieving near-optimal performance.
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关键词
high level synthesis,integer programming,linear programming,pipeline processing,processor scheduling,high-level synthesis,integer linear programming,loop iterations,loop pipelining,pipeline flushing,pipeline synthesis,pipelined execution
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