Low power pipelined SAR ADC with loading-free architecture

This paper presents a 12-bit 70-MS/s pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with loading-free architecture. This work proposes a loading-free concept of merging the feedback capacitor and the capacitor array of the second-stage SAR ADC to reduce op-amp output loading and area. In addition, the fixed-window function technique is used to reduce the power consumption and tolerate non-idealities in the first-stage SAR ADC. The ADC core occupies an active area of 0.117 mm2 in TSMC 90-nm 1P9M CMOS process. The measured results shows that the proposed ADC achieves 55.98 dB SNDR with 2.72 mW power consumption at 1 MHz input frequency.