21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS

Viki Szortyka,Qixian Shi,Kuba Raczkowski,Bertrand Parvais,Maarten Kuijk,Piet Wambacq

Solid-State Circuits Conference Digest of Technical Papers（2014）

引用 56|浏览25

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摘要

For high data-rate communication at 60GHz using the IEEE 802.11ad standard, the LO synthesis needs both a low-noise VCO and low in-band phase noise. In the PLL shown in this paper, a QVCO with superharmonic passive coupling exhibits a large swing and low phase noise even with a 0.9V supply. In-band phase noise is reduced thanks to the use of a sub-sampling phase detector (SSPD), earlier introduced for low-GHz PLLs [1]. As most of the divider chain and the charge pump (CP) can be powered down in the sub-sampling mode, power consumption is also reduced.

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关键词

cmos integrated circuits,charge pump circuits,field effect mimic,jitter,millimetre wave oscillators,phase detectors,phase locked loops,phase noise,telecommunication standards,voltage-controlled oscillators,wireless lan,cmos technology,ieee 802.11ad standard,lo synthesis,pll,qvco,sspd,charge pump,divider chain,frequency 60 ghz,in-band phase noise,low-noise vco,power 42 mw,size 40 nm,subsampling phase detector,superharmonic passive coupling,voltage 0.9 v

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