Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoSTM/3D ICs
VLSI-DAT（2014）
摘要
To meet power, performance and area requirements of modern electronic products, heterogeneous system integration where dies implemented in dedicated, optimized process technologies are stacked together to form a system is inevitable. The use of known-good pre-fabricated dies provides substantial reduction in time-to-market for integrated products. However, as dies from different suppliers using different technologies are used, finding source of design errors or manufacturing defects becomes very challenging if an integrated system fails in production. The system integrator has the onus to include test and diagnosis features that can enable post-silicon debugging. In this paper, we present a silicon diagnosis case study for a TSMC CoWoSTM based heterogeneous 3D chip. We demonstrate how the Design-for-Diagnosis features implemented on the logic die were used to isolate interconnects testing failures. We were not only able to speed up the diagnosis but also able to find the real source of failure, which was a design and modeling issue in one of the 3rd party known-good-die.
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关键词
elemental semiconductors,integrated circuit design,integrated circuit interconnections,integrated circuit reliability,integrated circuit testing,silicon,substrates,three-dimensional integrated circuits,si,tsmc cowos based heterogeneous 3d chip,area requirements,chip on wafer on substrate,design errors,design-for-diagnosis features,diagnosis features,electronic products,heterogeneous system integration,integrated products,interconnects testing failures,known-good prefabricated dies,logic die,manufacturing defects,optimized process technology,performance requirements,post-silicon debugging,power requirements,safety net,silicon diagnosis,test features,time-to-market reduction
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