First demonstration of strained SiGe nanowires TFETs with ION beyond 700µA/µm

A Villalon,Cyrille Le Royer,P Nguyen,S Barraud, F Glowacki,A Revelant,Luca Selmi,Sorin Cristoloveanu,L Tosti,C Vizioz,J M Hartmann, N Bernier,B Previtali,C Tabone,F Allain,S Martinie,O Rozeau,M Vinet

VLSI Technology（2014）

引用 34|浏览50

暂无评分

摘要

We present for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS-compatible process flow featuring compressively strained Si1-xGex (x=0, 0.2, 0.25) nanowires, Si0.7Ge0.3 Source and Drain and High-K/Metal gate. Nanowire architecture strongly improves electrostatics, while low bandgap channel (SiGe) provides increased band-to-band tunnel (BTBT) current to tackle low ON current challenges. We analyse the impact of these improvements on TFETs and compare them to MOSFET ones. Nanowire width scaling effects on TFET devices are also investigated, showing a W-3 dependence of ON current (ION) per wire. The fabricated devices exhibit higher ION than any previously reported TFET, with values up to 760μA/μm and average subthreshold slopes (SS) of less than 80mV/dec.

查看译文

关键词

cmos integrated circuits,ge-si alloys,mosfet,electrostatics,energy gap,field effect transistors,nanowires,tunnel transistors,btbt current,cmos-compatible process flow,ss,si,si0.75ge0.25,si0.7ge0.3,si0.8ge0.2,tfet devices,band-to-band tunnel current,bandgap channel,metal gate,nanowire architecture,nanowire tunnel fet,nanowire width scaling effects,strained nanowire tfet,subthreshold slopes,very large scale integration,logic gates,tunneling

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要