A 10Gb/s 4.1mW 2-IIR + 1-discrete-tap DFE in 28nm-LP CMOS
ESSCIRC（2014）
摘要
A half-rate decision feedback equalizer (DFE) with two infinite impulse response (IIR) filters and one discrete-time tap is presented. The two IIR filters have different time constants to cancel the long tail of the pulse response. The discrete-tap cancels the first post-cursor inter-symbol interference term. The system can operate with a low transmit swing of 150mVpp-diff and 24 dB channel loss at the Nyquist frequency while consuming 4.1mW at 10 Gb/s. The receiver, including the DFE, clock buffers and clock phase adjustment, occupies an area of 8,760 μm2 and was fabricated in an ST 28nm LP CMOS process.
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关键词
LP CMOS process,power 4.1 mW,CMOS integrated circuits,discrete-time tap,2-IIR-1-discrete-tap DFE,infinite impulse response filters,bit rate 10 Gbit/s,post-cursor intersymbol interference cancellation,size 28 nm,time constants,clock buffers,channel loss,low-power electronics,pulse response,clock phase adjustment,clocks,receivers,interference suppression,IIR filters,decision feedback equalisers,Nyquist frequency,intersymbol interference,channel estimation,half-rate decision feedback equalizer
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