A Reconfigurable 50-Mb/s-1 Gb/s Pulse Compression Radar Signal Processor With Offset Calibration in 90-nm CMOS
Microwave Theory and Techniques, IEEE Transactions （2015）
摘要
This paper presents a reconfigurable mixed-signal-processing circuit for high-speed pulse compression radar (PCR). Mixed-signal design techniques incorporate calibration and adaptation to improve the performance of a PCR receiver. Adaptive bandwidth PCR is an important feature for maximizing the dynamic range of a low-power radar system. The baseband signal processor includes a variable gain amplifier, 4-bit digital-to-analog converter, high-speed analog correlator, passive integrator, a 4-bit flash analog-to-digital converter, and a multi-range delay-locked loop. This proposed system is fabricated in 90-nm CMOS and can be configured to work from 50 Mb/s to 1 Gb/s with 2/3/5/7-bit Barker codes. The proposed calibration techniques improve the sidelobe reduction to 15.6 dB at 1 Gb/s. The total power consumption is 42 mW at the peak rate of 1 Gb/s for 15-cm range resolution.
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关键词
cmos analogue integrated circuits,cmos digital integrated circuits,amplifiers,analogue-digital conversion,delay lock loops,digital-analogue conversion,mixed analogue-digital integrated circuits,pulse compression,radar receivers,radar resolution,barker code,cmos,adaptive bandwidth pcr,baseband signal processor,bit rate 50 mbit/s to 1 gbit/s,digital-to-analog converter,flash analog-to-digital converter,high-speed pcr receiver,high-speed analog correlator,low-power radar system,multirange delay locked loop,offset calibration,passive integrator,power consumption,range resolution,reconfigurable mixed signal processing circuit,reconfigurable pulse compression radar signal processor,sidelobe reduction,size 90 nm,variable gain amplifier,analog correlation,dc-offset calibration,delay-locked loop (dll),flash analog-to-digital converter (adc),pulse compression radar (pcr),calibration,correlation,bandwidth
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