Frequency Response Mismatch Analysis in Time-Interleaved Analog I/Q Processing and ADCs

This paper examines a novel method to increase the usable analog bandwidth of analog-digital interface through the use of I/Q downconversion or Homodyne architecture followed by time-interleaved ADCs in both I and Q branches. The increased analog bandwidth comes with the inherent drawback of various spurious components, due to analog components’ frequency response mismatches, which ultimately limit the dynamic range. In this paper, the impacts of different mismatch sources are modeled and analyzed. Actual measured hardware data of the considered time-interleaved Homodyne architecture are also presented, verifying the modeling and analysis results. The analysis and modeling results of this paper provide thus new insight on the joint impact of different mismatch mechanisms and pave the way for future contributions on the correction of these mismatches, building on the derived composite behavioral model of the overall time-interleaved I/Q processing.