Design and Analysis of Inexact Floating-Point Adders

Power has become a key constraint in nanoscale inte-grated circuit design due to the increasing demands for mobile computing and higher integration density. As an emerging compu-tational paradigm, an inexact circuit offers a promising approach to significantly reduce both dynamic and static power dissipation for error-tolerant applications. In this paper, an inexact floating-point adder is proposed by approximately designing an exponent sub-tractor and mantissa adder. Related operations such as normaliza-tion and rounding are also dealt with in terms of inexact computing. An upper bound error analysis for the average case is presented to guide the inexact design; it shows that the inexact floating-point adder design is dependent on the application data range. High dynamic range images are then processed using the proposed inexact floating-point adders to show the validity of the inexact design; comparison results show that the proposed inexact floating-point adders can improve the power consumption and power-delay product by 29.98% and 39.60%, respectively.