Two-stage feedback-looped charge-pump for spur reduction in CMOS PLL

In this paper, two-stage charge pump is proposed for high performance phase-locked loop (PLL). Two-stage charge pump is to minimize the current mismatch and keeps the constant current across a wide range of output voltage. The charge pump is composed of the two-stage circuit which has the conventional push–pull charge pump and the compensation circuit. The compensation circuit has a feedback biasing circuit and an op-amp to act as a voltage follower. The proposed charge pump is applied in 2 GHz analog PLL to check out the noise spectrum of the spur and phase offset which are occurred from the current mismatch. PLL is designed with 0.18-µm CMOS process. In the post-layout simulation, the proposed charge pump indicates that the current mismatch is less than 5 % over the voltage range of 0.25–1.45 V which covers almost 70 % of the 1.8 V supply voltage. The spur in PLL is obtained to be −63.7 dBc with the power consumption of 13 mW.