SmartMig: A Case for Page Migration and Self-Interleaving for On-Chip Distributed Memory Systems
High Performance Computing and Communications, 2014 IEEE 6th Intl Symp Cyberspace Safety and Security, 2014 IEEE 11th Intl Conf Embedded Software and Syst(2014)
摘要
This paper tries to optimize the placements of data pages, which have a strong impact on system performance. We find that both core-to-memory distance and contention on MCs and interconnects are critical. Migrating pages to their page access center can mini-mize average memory access distance, but may cause serious contention and congestion, necessitating further schemes for load balancing. Based on these observations, we propose a novel runtime mechanism called SmartMig, in which we mi-grate data pages to shorten memory access distance, while employ page self-interleaving to balance the load across the nodes. We propose models and algorithms to decide the fate of candidate pages. Simulation results show that SmartMig achieves performance improvements by 26.9% and 21.0% in terms of normalized IPC and average memory access latency, which is a result of significant reduction of core-to memory distance and load in balance.
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关键词
core-to-memory distance,self-interleaving,on-chip distributed memory systems,migration,on-chip distributed memory system,distributed memory systems,storage management,runtime mechanism,page self-interleaving,data placement,page migration,memory access latency,smartmig,memory access distance,paged storage,load balancing,system on chip,routing
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