FPGA power and timing optimization: architecture, process, and CAD
Computational Problem-Solving（2010）
摘要
Field programmable gate arrays (FPGAs) allow the same silicon implementation to be programmed or reprogrammed for a variety of applications. It provides low NRE (non-recurring engineering) cost and short time to market. As CMOS technology continue to scale down to nanometer, increased power consumption and worsened process variation become crucial constraints for FPGAs. The survey reviews the process and architecture evaluation and CAD algorithms to optimize power and delay for FPGAs.
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关键词
cmos integrated circuits,cad,power consumption,fpga power,cad algorithms,architecture evaluation,circuit optimisation,timing optimization,low-power electronics,low nre cost,cmos technology,nonrecurring engineering,field programmable gate arrays,switches,routing,logic gates,low power electronics,process variation,design automation,field programmable gate array,strontium
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