Investigation and implementing gate resistance testing for power MOSFET device

For power MOSFET, the switching performance is very important for its application and greatly depends on the product of the gate resistance (Rg) and the input capacitance (Ciss). This paper presents the characteristics and modeling of gate resistance based on the power DMOS device, and gives an analysis of each of the components of Rg, such as gate polysilicon resistance, channel resistance, source resistance and package bonding wire resistance, based on their electrical properties. Also we will present its effect on the switching performance of power MOSFET during gate charge-discharge and the resulting switching frequency. Through a series of testing experiments with variable testing voltage, frequency and DC bias, an optimum Rg testing methodology is developed for device characterization. Under such condition, with enough negative DC bias for N type DMOS and positive DC bias for P type DMOS, the device is in accumulation state, and a small AC signal with the frequency over 1MHZ, a stable Rg value can be obtained. Using this Rg testing method, many of the chip fabrication and package processes induced defects can be successfully identified. Many of the device and packaging processing related yield defective problems can be discovered. In this paper we will describe some of the device fabrication related issues, such as improper ion implantation of poly gate doping, poor gate suicide formation and the metal contact defects, and the wire bonding problems in the packaging process, such as bonding lift and heel crack of the gate wire for power MOSFET. These defects are difficult to discover through a general DC measurement method but can be identified through the Rg test we developed. More detail discussion of the cause of those yield related issues and measurement results are discussed in our paper.