An 11-Bit Enob, Accuracy-Programmable, And Non-Calibrating Time-Mode Sar Adc

A 10 or 12 bit programmable successive approximation register (SAR) ADC incorporating improved time-domain comparator for bridge stress monitoring systems is presented. Techniques for improving the accuracy of time-domain comparator are presented. The application of these approaches is illustrated using results from an experimental 10 or 12 bit programmable SAR ADC. Prototyped in a 0.18-mu m, 6M1P CMOS process, the ADC, at 12 bit, 100 kS/s, achieves a Nyquist signal-to-noise-plus-distortion ratio (SNDR) of 68 dB (11 ENOB), a spurious free dynamic range (SFDR) of 77.48 dB, while dissipating 558 mu W from a 1.8-V supply. Its differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.2/-0.74 LSB and + 1.27/-0.97 LSB, respectively.