A computation and storage trade-off in mapping 2-d convolution networks on field programmable gate arrays

Two-dimensional (2-D) convolution networks are widely used in pattern recognition and intelligent text applications. Depending on the size of input image and convolution kernel, the 2-D convolution can require significant amounts of calculation, thus suggesting that the actual operation is both compute-extensive and memoryextensive. Multiplyaccumulate (MAC) based Field-programmablegate-array (FPGA) parallel processing architectures were proposed to accelerate calculations for the 2-D convolution. And data buffering implemented with FPGA onchip resources was used to reduce the offchip memory bandwidth requirement. In this paper, we present a computation trade-off involved in mapping 2-D convolution networks on an FPGA device. Compared with the previous methods, the new scheme exhibits a good balance between computation resource and off-chip memory bandwidth utilization, and therefore is suitable for FPGA-based implementation. © 2013 ICIC International.