Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM

Shao-Cheng Wang,Geng-Cing Lin,Yi-Wei Lin,Ming-Chien Tsai,Yi-Wei Chiu,Shyh-Jye Jou,Ching-Te Chuang,Nan-Chun Lien,Wei-Chiang Shih,Kuen-Di Lee,Jyun-Kai Chu

APCCAS（2012）

引用 3|浏览26

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摘要

We present an all-digital monitor structure to measure the Write Margin (WM) with dynamic Word-Line (WL) pulse for standard CMOS 6T SRAM. Ring oscillator and frequency divider based structures are used to generate wide range WL pulses (150ps ~ 32ns) with resolution of 50ps. The bit-line voltage is then successively stepped down for dynamic Write Margin characterization under given word-line pulse width. An improved Skitter based structure is employed to measure the WL pulse width with resolution of 10 ~ 20ps. Implementation of a 256Kb test chip in UMC 55nm Standard Performance (SP) CMOS technology is described.

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关键词

cmos 6t sram,dynamic write margin characterization,sram chips,frequency divider based structure,all-digital monitor structure,size 55 nm,ring oscillator,dynamic word-line pulse write margin monitor,umc standard performance cmos technology,frequency dividers,skitter based structure,memory size 6 tbyte,write margin measurement,memory size 256 kbyte,oscillators,cmos memory circuits

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