Defect tolerance at the end of the roadmap
Nano, quantum and molecular computing(2003)
摘要
As feature sizes shrink closer to single digit nanometer dimensions, defect tolerance will become increasingly important. This is true whether the chips are manufactured using top-down methods, such as photolithography, or bottom-up assembly processes such as Chemically Assembled Electronic Nanotechnology (CAEN). In this chapter, we examine the consequences of this increased rate of defects, and describe a defect tolerance methodology centered around reconfigurable devices, a scalable testing method, and dynamic place-and-route. We summarize some of our own results in this area as well as those of others, and enumerate some future research directions required to make nanometer-scale computing a reality.
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关键词
chemically assembled electronic nanotechnology,defect tolerance,own result,bottom-up assembly,feature size,future research direction,reconfigurable device,dynamic place-and-route,defect tolerance methodology,increased rate,top down,chip,place and route,switches,manufacturing,bottom up,field programmable gate arrays,lithography,test methods
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