Ultra-Thin Body And Buried Oxide (Utbb) Fdsoi Technology With Low Variability And Power Management Capability For 22 Nm Node And Below

In this paper, we present the comparison of Silicon on Insulator (SOI) Ultra-Thin Body and Buried Oxide (UTBB) substrates with two different back planes (BP) designed to address Low Leakage (LL) and High Speed (HS) Static Random-Access Memory (SRAM) bitcells. The power management capability is analyzed for both n-and p-type BP. We demonstrate that the back biasing does not induce any degradation of the VT variability (maintained at A(VT) = 1.4 mV.mu m)on each BP and enables improving the ISAT/IOFF characteristics. This excellent variability is transferred in SRAM Noise Margin (SNM) in read mode where low minimum operating supply voltages (VMIN) below 0.6 V are demonstrated. Thanks to the back biasing, it is possible to achieve 26% bitcell read current (ICELL) improvement with 6% standby leakage current (ISB) reduction when the substrate voltage (VB) is equal to 0.9 V (on a p-type BP). Finally, due to low sigma(SNM) and large mu(SNM) changes with VB, the SNM/sigma(SNM) ratio (and thus VMIN) can be optimized, up to a factor of 30% and 68% when VB = -0.9 V, respectively for p-and n-type BP.