FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis.

Time-division multiplexed (TDM) wiring is explored to increase the capacity of FPGA wiring channels while decreasing the silicon area. More efficient use of hard IP blocks is made possible by time multiplexing them in conjunction with TDM data transport. Look-up table utilization is reduced through automatic serialization of system-on-FPGA interconnect and off-chip communication. Our scheduling tool is able to share wires effectively and reduce the amount of wiring required on the FPGA. The wiring is clocked many times faster than the user clock so the signals can be pipelined and the wires shared without changing the functionality of the circuit. Previous work using an earlier version of our tool showed that wiring reductions were possible, but it is only now we have shown them to be practical. Important improvements to this work have included the move from bidirectional to unidirectional wires. There is also no longer a mix of TDM and static wiring: all wires are shared, but not necessarily pipelined. The scheduling tool trades-off between effective wire sharing and critical path delay. Following these changes the wiring was redesigned to encode configuration bits more efficiently and reduce the silicon area. This transistor-level model of the wiring was used to estimate the silicon area of our new TDM architecture. Our results indicate that the amount of wiring required can be reduced by as much as 82% whilst running the interconnect clock 16 times faster than the user clock. The interconnect cycles through 16 wiring configurations every user clock cycle. Area estimations indicate that this wire reduction is sufficient to reduce the silicon area, despite the extra configuration SRAM. This reduction in silicon area comes with an increase in channel routing capacity.