An Enhanced Edac Methodology For Low Power Psram

As feature size keeps shrinking, how to maintain the reliability becomes an important issue in IC production, especially for high density memory circuits. Error detection and correction (EDAC) schemes have been widely used for memory circuits for this purpose, but ordinary EDAC schemes are not suitable for memories with long codewords. The demand for low-power memory is increasing due to the growth in portable electronics markets. Power reduction in memories with DRAM-like cells can be done by reducing the refresh frequency, but the loss of data integrity should be taken care of seriously. To solve the above two issues, we propose a parallel encoding and decoding EDAC scheme, which can be used on memories with long codewords. Targeting refresh power reduction, we have implemented our scheme on an industrial pseudo SRAM (PSRAM), and have completed experiments. The major hardware penalty is the parity overhead that is 1/9, and the longest delay of our circuit is 3.6ns for the PSRAM fabricated by a 0.11 mu m CMOS technology. With respect to the 70ns access time of the PSRAM, the proposed EDAC scheme can be integrated with the Read/Write operations without increasing the latency. Experimental results show that the refresh time can be extended greatly, without sacrificing reliability.