A Study Of Improving Fetch And Execute Engine For Simultaneous Multithreading Processors

Simultaneous Multithreading (SMT) is a single processor design technique that attempts to combine both the hardware features of conventional superscalar and multithreading processors. The purpose is to exploit the Instruction-Level Parallelism (ILP) and Thread-Level Parallelism (TLP) dynamically. The fetch unit has been identified as one of the major bottlenecks of SMT architecture and has been studied wildly. However, only a few studies focused on the SMT processor issue buffer and issue scheme.In this paper, we propose a novel fetch policy and issue scheme based on distributed instruction queuing buffer. We added per-thread counter called Ready Instruction Count (RIC) as base of issue scheme. Simulation results show that Our method can improve performance by 18.9% over baseline. Furthermore, due to structure hazard, we design a RIC scheduler to mange and arbitrate the use of shared hardware resources. Finally, we discuss the load balance on SMT architecture.