A unified hardware-software framework for evaluating power consumption of embedded system-on-a-chip designs

Recent years have seen a tremendous growth in both the complexity and demand for embedded computing systems. The rapid increase in design complexity combined with stringent time-to-market requirements has resulted in a need for computer aided design (CAD) tools that can help to make fundamental decisions as early as possible in the design cycle. In this thesis we developed a framework to efficiently estimate power consumption of embedded System-on-a-Chip (SOC) designs at the system level. Most work to date has focused on the component level, rather than the system level. In these techniques, power consumption is estimated by associating to each component of the system a power model, which is obtained by pre-characterization either at the gate level or at the transistor level. Unfortunately, in order to perform a gate level or a transistor level characterization, a detailed knowledge of the components' internal structure is needed. At the early stage of the design cycle, such information may not be available or intellectual properties (IP) providers may not want to disclose it. The major contribution of this thesis is to overcome this deficiency. We propose an estimation technique in which the power figures associated to each component of the system are derived from the execution of high level models rather than gate-level or transistor level pre-characterizations. The chief benefit is that design assessment can be done much earlier in the design cycle. As a consequence, engineers can be assisted in their decision-making process from the very beginning of the system design cycle. The use of a higher level of abstraction also leads to approximately three orders of magnitude speedup of the estimation time. We have compared our system-level approach against gate level simulation and actual measurements on the real hardware. The results are within 10% of the gate level and physical measurement.