The impact of interface/border defect on performance and reliability of high-k/metal-gate CMOSFET.

The impact of interface/border defect on performance and reliability was investigated for gate-first and gate-last high-k/metal-gate CMOSFET. For high-k/metal-gate CMOSFET, VFB roll-off is critical as effective oxide thickness (EOT) scales below 15 angstrom (Å) especially for metal gate-first device with an extra capping layer to adjust VTH. By proposing a model of metal-gate process induced interface trap releasing oxygen, the vertical and lateral interface trap distribution and the dependence of interfacial layer (IL) on VFB roll-off phenomena can be well interpreted. In this work, we found that VFB roll-off can be improved by reducing oxygen vacancy (VO) at the HfO2/IL interface with suppression of oxygen diffusion from high-k to IL. By the way, a metal gate-last process with lower interface trap was proposed to minimize VO formation by suppress oxygen releasing, thus optimize a 28nm 15Å EOT HfO2/metal-gate CMOSFET with low VFB–EOT roll-off, it can be a reference for sub 22nm CMOSFET with thin EOT (<15Å) design.