Abstract: Configuration Relocation and Defragmentation for Reconfigurable Computing1

Custom computing systems exhibit significant speedups over traditional microprocessors by mapping compute- intensive sections of a program to reconf igurable logic (Hauck98). However, the high overhead of reconfiguration can limit the execution times achievable with these systems. Research has shown that the ability to relocate and defragment configurations on an FPGA dramatically decreases the overall configuration overhead (Li00). We therefore explore the adaptation of the Xilinx 6200 series FPGA for relocation and defragmentation. Due to some of the complexities involved with this structure, we also present a novel architecture designed from the ground up to provide relocation and defragmentation support with a negligible area increase over a generic partially reconfigurable FPGA. Relocation and Defragmentation The basic partially reconfigurable FPGA design is powerful, but it faces limitations imposed by configuration locations determined at compile time. If two different configurations were mapped at compile time to overlapping locations in the FPGA, they can not be used simultaneously. The ability to relocate one or both of these configurations to a new location might allow for concurrent use. Defragmentation extends this idea to move the configurations already present on the FPGA to new locations, consolidating unused area. Therefore, an incoming configuration may be able to be programmed onto the FPGA without removing any of the configurations already present.