Power analysis of gated pipeline registers
Washington, DC（1999）
摘要
System-on-chip (SoC) is becoming a reality as industry begin to combine a wide range of complex functionalities on a single die. System power optimization becomes an important issue in ensuring practical packaging and system reliability. In this paper, we measure the benefits of using clock gating on pipeline registers in a RISC datapath. Different pipeline register fields are gated by different already available control signals. The architectural level simulation results show that this technique can effectively reduce switch capacitance by 55.2% for pipeline registers and 22.1% for the datapath on average
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关键词
packaging,logic simulation,gated pipeline registers,reduced instruction set computing,switch capacitance reduction,circuit optimisation,low-power electronics,shift registers,system-on-chip,clock gating,architectural level simulation,clocks,power analysis,integrated circuit design,pipeline register fields,system reliability,flip-flops,system power optimization,d flip-flop,risc datapath,pipeline processing,system on chip,switches,low power electronics,reliability engineering,registers,power optimization,capacitance,pipelines
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