A Divided Decoder-Matrix (Ddm) Structure And Its Application To A 8kb Gaas Mesfet Rom

Riad Kanan,Alain Guyot,Bertrand Hochet,Michel Declercq

ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE（1997）

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摘要

This paper describes a new approach which allows the realization of both low-power and high storage capacity ROMs in GaAs. In this technique, called DDM (Divided Decoder Matrix), low-power operation is obtained by powering down the parts which are not situated in the addressing path, while high-storage capability is obtained by limiting the leakage currents in the ROM matrix,As an application of the DDM technique, an 8Kbit MESFET ROM has been designed with a standard 0.6 mu m-gate MESFET process, The ROM has a typical access time of 1.2 ns and a power dissipation of 60 mW.

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关键词

iii-v semiconductors,mesfet integrated circuits,decoding,field effect memory circuits,gallium arsenide,leakage currents,random-access storage,0.6 micron,1.2 ns,60 mw,8 kbit,gaas,gaas mesfet rom,rom matrix,divided decoder-matrix structure,high storage capacity roms,leakage current limitation,low-power roms,low-power operation,power dissipation,very large scale integration,read only memory,logic,leakage current

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