Median Biased Steiner Tree Heuristics in the Rectilinear Plane for Low-Power Physical Layout
MWSCAS '98 Proceedings of the 1998 Midwest Symposium on Systems and Circuits（1998）
摘要
Two heuristics are proposed for the rectilinear Steiner minimum tree (SMT) problem arising when interconnecting multiple terminals in a layout with obstacles. Efficient algorithms are implemented to convert circuit layouts into graphs. A set of reduction techniques are implemented to remove unfeasible vertices from layout graphs. These techniques delete an average of over 90% of the m Steiner candidates in O(m^2) time. The proposed SMT heuristics grow trees biased by the terminal distances of the n vertices in a graph in O(n^2 log n) time. The results obtained highlight their suitability to be used as wire length estimators in a power optimizing placement tool.
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关键词
rectilinear steiner minimum tree,layout graph,n vertex,proposed smt heuristics,rectilinear plane,low-power physical layout,circuit layout,m steiner candidate,placement tool,interconnecting multiple terminal,efficient algorithm,log n,median biased steiner tree,capacitance,power optimization,integrated circuit layout,steiner trees,network topology,low power electronics,tree graphs,routing,vlsi,very large scale integration,steiner tree
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