3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs
DATE（2012）
摘要
Three-dimensional (3D) circuit integration is a promising technology to alleviate performance and power related issues raised by interconnects in nanometer CMOS. Physical planning of three-dimensional integrated circuits is substantially different from that of traditional planar integrated circuits, due to the presence of multiple layers of dies. To realize the full potential offered by three-dimensional integration, it is necessary to take physical information into consideration at higher-levels of the design abstraction for 3D ICs. This paper proposes an incremental system-level synthesis framework that tightly integrates behavioral synthesis of modules into the layer assignment and floorplan- ning stage of 3D IC design. Behavioral synthesis is implemented as a sub-routine to be called to adjust delay/power/variability/area of circuit modules during the physical planning process. Experimental results show that with the proposed synthesis-during-planning methodology, the overall timing yield is improved by 8%, and the chip peak temperature reduced by 6.6°C, compared to the conventional planning-after-synthesis approach.
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关键词
three-dimensional integrated circuit planning,cmos integrated circuits,integrated circuit interconnections,physical planning,circuit module,nanometer-scale cmos interconnects,ic design,3d high level synthesis,floorplanning,variability adjustment,three-dimensional ic,physical planning process,three-dimensional circuit integration,behavioral synthesis,three-dimensional integrated circuits,delay adjustment,design abstraction,3dhls,power adjustment,synthesis-during-planning methodology,layer assignment,circuit modules,multiple die layers,circuit integration,area adjustment,three-dimensional integrated circuit,integrated circuit layout,physical information,high-level synthesis,high level synthesis,nanoelectronics,3d ic design,incremental system-level synthesis framework,integrated circuits,integrated circuit,signal to noise ratio,approximation error,three dimensional,chip,lead
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