A 14b extended counting ADC implemented in a 24Mpixel APS-C CMOS image sensor
ISSCC(2012)
摘要
The demand for high-quality and high-speed imaging has increased. Column-parallel ≥14b A/D conversion is one of the major approaches to meet these requirements in CMOS image sensors (CIS). Oversampling ADCs such as incremental delta-sigma (I-ΔΣ) ADCs are the solution for a high-resolution ADC having tolerance of analog component errors. Oversampling reduces input temporal noise as well as the quantization error of the ADC itself [1]. However, an I-ΔΣ ADC is also classified as a slow ADC because it requires exponential conversion time to get higher bit resolution. To reduce conversion time, there are two alternative methods: 1) higher-order modulation, and 2) two-step conversion such as an extended-counting technique [2]. In this paper, the extended-counting (EC) method is used since a high-order structure requires more complex hardware and greater power consumption [1,2]. For a general two-step ADC, coarse conversion restricts the total ADC resolution since it determines accuracy of the residue. However, an EC ADC overcomes the accuracy limitation, since the I-ΔΣ can improve its precision through oversampling. Moreover, oversampling also suppresses the noise of the pixel's source follower. Our 14b EC ADC is a blend of a 1st-order I-ΔΣ ADC and a cyclic ADC to simultaneously get high resolution and high speed.
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关键词
i-δς adc,cyclic adc,higher-order modulation,power consumption,analogue-digital conversion,cmos image sensors,high-quality imaging,high-speed imaging,analog component errors,quantization error,delta-sigma adc,14b ec adc,delta-sigma modulation,extended-counting method,24mpixel aps-c cmos image sensor,two-step conversion,two-step adc,input temporal noise,14b extended counting adc,1st-order i-δς adc,high-resolution adc,cis,image resolution,delta sigma modulation,higher order,noise,high resolution,noise measurement,cmos image sensor
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