SHard: a Scheme to Hardware Compiler

Implementing computations in hardware can offer better perfor- mance and power consumption than a software implementation, typically at a higher development cost. Current hardware/software co-design methodologies usually start from a pure software model that is incrementally transformed into hardware until the r equired performance is achieved. This is often a manual process which is tedious and which makes component transformation and reuse dif- ficult. We describe a prototype compiler that compiles a func tional subset of the Scheme language into synthesizable descriptions of dataflow parallel hardware. The compiler supports tail and n on- tail function calls and higher-order functions. Our approa ch makes it possible for software developers to use a single programming language to implement algorithms as hardware components using standardized interfaces that reduce the need for expertise in digital circuits. Performance results of our system on a few test programs are given for FPGA hardware.