Minimizing The Error: A Study Of The Implementation Of An Integer Split-Radix Fft On An Fpga For Medical Imaging

Fixed-point arithmetic is used to provide faster and smaller implementations in many digital signal processing applications, including medical imaging, at the expense of decreased accuracy. In particular, when a Fast Fourier Transform (FFT)-Inverse Fast Fourier Transform (IFFT) pair are required as part of the calculation, the error introduced into the calculations can be significant. For some applications, such as Fourier Domain Optical Coherence Tomography (FD-OCT), this degradation is unacceptable. Our study shows that using a conventional fixed-point FFT-IFFT pair, such as Xilinx's FFT core, can produce an average 6-bit error for a 1024-point FFT using 12-bit input data in a 32-bit arithmetic system. The majority of the error is caused by quantization effects, particularly on the phase information of input signal. For this reason, in phase sensitive applications such as FD-OCT, the error dominates the fixed-point calculation: 78% in 16-bit and 51% in 32-bit systems.This work presents a parameterized 32 to 4096-point integer FFT implementation for FPGAs that uses a Split-Radix algorithm to reduce the number of multiplies and improve latency. Integer FFTs are perfectly reconstructible, with zero reconstruction error. Here, we specifically analyze a 1024-point Integer Split-Radix FFT (Int-SRFFT) and IFFT pair that perfectly reconstructs the original 12-bit input data using 22-bit arithmetic, compared to the average 6-bit error for a 1024-point FFT using 32-bit fixed-point arithmetic. The pipelined architecture of this design has a latency of 29.06us for a 1024-point FFT, and a throughput of more than 34 thousand 1024-point FFTs/second for a 22-bit datapath at an operating frequency of 274MHz. Although our Int-SRFFT is perfectly reconstructible, compared to Xilinx's fixed-point FFT, it has similar to 6% more flipflops, similar to 63% more LUTs, 5.3x more BRAMs, and a similar to 44% increase in latency. However, compared to a previous fixed-point SRFFT design on an FPGA, our throughput is 15.5x greater.