Hybrid CMOS/Nanodevice Integrated Circuits for Digital Electronics: CMOL Approach

ITRS 2005 (1) predicts that due to problems of CMOS scaling, some time during the next decade the continuation of Moore's-Law progress of semiconductor electronics will require the transfer to hybrid VLSI circuits based on heterogeneous device technologies including, but not limited to CMOS. Our group has suggested (2, 3) the so-called "CMOL" version of such hybrid circuits that avoids problems pertinent to earlier hybrid circuit suggestions - see, e.g., Ref. 3 for their review. The basic idea of CMOL circuits is to combine the advantages of CMOS technology (with its flexibility and high fabrication yield) with those of molecular-scale nanodevices. Two- terminal nanodevices would be naturally incorporated into nanowire crossbar fabric, enabling very high function density at acceptable fabrication costs. In order to overcome the CMOS/nanodevice interface problem, in CMOL circuits the interface is provided by sharp-tipped pins that are distributed all over the circuit area, on top of the CMOS stack. The most straightforward possible application of CMOL circuits is terabit-scale "resistive" memories (2, 3), in which nanodevices (e.g., single molecules) would be used as single-bit memory cells, while the semiconductor subsystem would perform all the peripheral (input/output, coding/decoding, line driving, and sense amplification) functions. Using bad-bit exclusion and error-correcting codes synergistically we show that CMOL memories with a nano/CMOS pitch ratio close to 1/3 may overcome purely semiconductor memories in useful density if the fraction of bad nanodevices is below ~15%, even for the 30 ns upper bound on the total access time. As the nanotechnology matures, and the pitch ratio approaches an order of magnitude, the CMOL memories may be far superior to the densest semiconductor memories by providing, e.g., 1 Tbit/cm 2 density even for the plausible defect fraction of 2%. Even greater defect tolerance (about 20% for 99% circuit yield) can be achieved in uniform a cell-FPGA-like CMOL circuits (2, 3). In such circuits, two- terminal nanodevices provide programmable diode functionality for logic circuit operation, and allow circuit mapping and reconfiguration around defective nanodevices, while CMOS subsystem is used for signal restoration and latching. To evaluate the potential performance of CMOL FPGA