An Architecture for Large ModSAF Simulations Using Scalable Parallel Processors

An implementation of ModSAF for Scalable Parallel Processors (SPPs) is presented. This model ex- ploits the large number of processing elements and fast interprocessor communications of SPPs to simulate many thousands of vehicles on a single SPP. The implementation uses a heterogeneous assignment of tasks to processors, with most processors running independent copies of the standard SAFSim code and additional processors used as either data servers or message routers. The key element of the architecture is the collection of router processors that move interest-restricted messages among the individual SAFSims at rates far higher than usually seen for ModSAF runs with networked workstations. The router architecture has been implemented using the standardized and portable Message Passing Interface (MPI) and has been run successfully on a variety of different platforms. The scaling behav- ior of the model is analyzed and measured performance results are presented for runs involving up to 16,000 simulated vehicles. Generalizations of the currently used interest management rules (based on ModSAF 2.1) to the more effective Data Distribution Management procedures developed for recent STOW exercises are discussed. Differences and simi- larities between this work and ongoing RTI-s and STOW communications network activities are also noted.