Not Necessarily More Switches More Routability

It has been observed experimentally that the mapping of global to detailed routing in conventional FPGA routing architecture (2D array) yields unpredictable results, In [8,10,13], a different class of FPGA structures called Greedy Routing Architectures (GRAs), where a locally optimal switch box routing can be extended to an optimal entire chip routing, were investigated, It was shown that GRAs have good mapping properties, An H-tree GRA [10] with W-2+2W switches per switch box (SpSB) and a 2D array GRA [13] with 4W(2)+2W SpSB were proposed (W is the number of tracks in each switch box), Here, we continue this work by introducing an H-tree GRA with W-2/2+2W SpSB and a 2D array GRA with 3.5W(2)+2W SpSB, These new GRAs have the same good mapping properties but use fewer switches, We also show a class of FPGA architectures in which the mapping problem remains NP-complete, even with 6(W-1)(2)+6W(2) SpSB, This is close to the maximum number of SpSB which is 6W(2).